Advance semiconductor processing techniques currently employed often involve the use of multiple metallization layers. These layers are used to interconnect active devices in a semiconductor circuit. Metal traces formed in the metallization layers also must be interconnected in order to pass signals from one metal layer to the next. Interconnections between the metallization layers are typically accomplished through the formation of conductive vias or plugs between the metal layers.
FIG. 1 illustrates an example of an interconnect structure 10 formed by a plug 14 between a Metal 1 (M1) layer 16 and a Metal 2 (M2) layer 12. The metal layers are typically composed of aluminum while the plug 14 is typically formed using a different type of conductive material such as tungsten. Because the plug 14 is a formed from a different material using a different fabrication step, there are two interfaces formed which have resistance associated with them: the interface I1 between the plug and Metal 1 and the interface I2 between the plug and Metal 2.
FIGS. 2A-C illustrate a typical example of the process for forming plug 14. Once the Metal 1 layer 16 has been formed on a semiconductor substrate (not shown), an inter-metal dielectric (IMD) layer 20 is formed on top of the Metal 1 layer and etched to form a trough 22, as shown in FIG. 2A. A tungsten layer 24 is then formed on top of the IMD layer 20 which fills the trench to form the plug 14, as shown in FIG. 2B. The tungsten layer 24 is then lapped, through a process such as chemical-mechanical polishing (CMP), or etched-back to remove the excess tungsten but, ideally, leaving the trough filled with tungsten to form plug 14. The Metal 2 layer 16 is then formed on top of the IMD layer 20 and the plug 14.
However, variations and errors in processing parameters causes large variations in the resistance of the plug 14 and the interfaces I1 and I2. For instance, excessive amounts of chemical or pressure in a CMP polishing step may remove too much tungsten material from plug 14 resulting in a depression or divot at the interface between the plug and the metallization layer formed on top of the plug and its associated IMD layer. The metal protruding into the divot at the top of the plug has greater surface contact area with the plug than would a normal plug that was flush with the surface of the IMD layer. If, however, the divot is sufficiently large, then the loss of conductive material in the plug can lead to greater resistance of the plug itself. These problems can be detected by observing the resistance of the I2 interface.
Also, vias or plugs are often stacked on top of one another in successive metallization layers. As a result, problems in earlier processing steps can accumulate in the upper metallization layers causing variations in the plugs between the upper metallization layers and often result in voids, such as void 26 illustrated in FIG. 2C, in these upper layer plugs. A void or trough in a plug can be detected through measurement of the resistance of the plug itself.
The resistance of plugs is typically measured to detect problems with the plugs, such as those described above, arising during the manufacturing process. FIG. 3 illustrates a top view of the structure typically used to measure the resistance of a plug. The M1 layer 16 has two pads A and C that are externally accessible for the purposes of test. The M2 layer 12 also has two pads B and D that are externally accessible for the purposes of test. The plug 14 interconnects the M1 layer 16 to the M2 layer 12.
In the conventional structure of FIG. 3, two measurements are typically taken. For the first measurement, a current source is coupled between pads A and B and the voltage is measured between pads C and D to obtain the cumulative resistance of plug 14 and the interfaces I1 and I2. Then the process is repeated with the current source coupled between pads C and D and the voltage measured between pads A and B. The two measurements are averaged to compensate for the variations in trace length between the plug and the four pads and the test probe contacts to the pads.
The structure of FIG. 3 and the method just described are limited to measuring the cumulative resistance of the plug and the interfaces I1 and I2 shown in FIG. 1. No information is obtained from the test measurements that will indicate whether a resistance problem lies with either of the two interfaces I1 and I2 or with the plug itself. As a result, the source of a problem with the via resistance must be guessed at in what is usually an expensive and complex semiconductor fabrication process.
Accordingly, a need remains for a structure and method for obtaining separate resistance measurements for the plug and metal interfaces of an inter-metal layer via.